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ACS573HMSR中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

ACS573HMSR
廠商型號(hào)

ACS573HMSR

功能描述

Radiation Hardened Octal Three-State Transparent Latch

文件大小

45.5 Kbytes

頁(yè)面數(shù)量

4 頁(yè)

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡(jiǎn)稱(chēng)

Intersil

中文名稱(chēng)

Intersil Corporation官網(wǎng)

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更新時(shí)間

2025-3-18 17:30:00

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ACS573HMSR規(guī)格書(shū)詳情

Description

The Intersil ACS573MS is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable (LE) is High. When the latch goes low the data is latched. The output enable controls the three-state outputs.

Features

? Devices QML Qualified in Accordance with MIL-PRF-38535

? Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96724 and Intersil’s QM Plan

? 1.25 Micron Radiation Hardened SOS CMOS

? Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

? Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)

? SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg

? Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse

? Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse

? Latch-Up Free Under Any Conditions

? Military Temperature Range . . . . . . . . . . . . . . . . . . -55°C to +125°C

? Significant Power Reduction Compared to ALSTTL Logic

? DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 30 of VCC Max

??? - VIH = 70 of VCC Min

? Input Current ≤ 1μA at VOL, VOH

? Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)

產(chǎn)品屬性

  • 型號(hào):

    ACS573HMSR

  • 制造商:

    INTERSIL

  • 制造商全稱(chēng):

    Intersil Corporation

  • 功能描述:

    Radiation Hardened Octal Three-State Transparent Latch

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