AD9515集成電路（IC）的時鐘緩沖器驅(qū)動器規(guī)格書PDF中文資料

AD9515屬于集成電路（IC）的時鐘緩沖器驅(qū)動器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9515時鐘緩沖器，驅(qū)動器時鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負(fù)載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。

GENERAL DESCRIPTION

The AD9515 features a two-output clock distribution IC in a

design that emphasizes low jitter and phase noise to maximize

data converter performance. Other applications with

demanding phase noise and jitter requirements also benefit

from this part.

There are two independent clock outputs. One output is

LVPECL, while the other output can be set to either LVDS or

CMOS levels. The LVPECL output operates to 1.6 GHz. The

other output operates to 800 MHz in LVDS mode and to

250 MHz in CMOS mode.

Each output has a programmable divider that can be set to

divide by a selected set of integers ranging from 1 to 32. The

phase of one clock output relative to the other clock output can

be set by means of a divider phase select function that serves as

a coarse timing adjustment.

The LVDS/CMOS output features a delay element with three

selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each

with 16 steps of fine adjustment.

The AD9515 does not require an external controller for

operation or setup. The device is programmed by means of

11 pins (S0 to S10) using 4-level logic. The programming pins

are internally biased to ? VS. The VREF pin provides a level of

? VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.

The AD9515 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9515 is available in a 32-lead LFCSP and operates from

a single 3.3 V supply. The temperature range is ?40°C to +85°C.

FEATURES

1.6 GHz differential clock input

2 programmable dividers

Divide-by in range from1 to 32

Phase select for coarse delay adjust

1.6 GHz LVPECL clock output

Additive output jitter 225 fs rms

800 MHz/250 MHz LVDS/CMOS clock output

Additive output jitter 300 fs rms/290 fs rms

Time delays up to 10 ns

Device configured with 4-level logic pins

Space-saving, 32-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

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