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ADN2807_V01中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

ADN2807_V01
廠商型號

ADN2807_V01

功能描述

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amplifier

文件大小

354.46 Kbytes

頁面數(shù)量

21

生產(chǎn)廠商 Analog Devices
企業(yè)簡稱

AD亞德諾

中文名稱

亞德諾半導體技術有限公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-20 22:04:00

ADN2807_V01規(guī)格書詳情

FEATURES

Meets SONET requirements for jitter transfer/ generation/tolerance

Quantizer sensitivity: 4 mV typical

Adjustable slice level: ±100 mV

Patented clock recovery architecture

Loss-of-signal detect range: 3 mV to 15 mV

Single-reference clock frequency for all rates, including 15/14 (7%) wrapper rate

Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK

REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible (LVPECL/LVDS only at 155.52 MHz)

Optional 19.44 MHz on-chip oscillator to be used with external crystal

Loss-of-lock indicator

Loopback mode for high speed test data

Output squelch and bypass features

Single-supply operation: 3.3 V

Low power: 540 mW typical

7 mm × 7 mm, 48-lead LFCSP

APPLICATIONS

SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates

WDM transponders

Regenerators/repeaters

Test equipment

Passive optical networks

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