C505-2R中文資料英飛凌數(shù)據(jù)手冊PDF規(guī)格書

Advance Information

Features

? Fully compatible to standard 8051 microcontroller

? Superset of the 8051 architecture with 8 datapointers

? Up to 20 MHz operating frequency

– 375 ns instruction cycle time @16 MHz

– 300 ns instruction cycle time @20 MHz (50 duty cycle)

? On-chip program memory (with optional memory protection)

– C505(C)(A)-2R : 16K byte on-chip ROM

– C505A-4R/C505CA-4R: 32K byte on-chip ROM

– C505A-4E/C505CA-4E: 32K byte on-chip OTP

– alternatively up to 64k byte external program memory

? 256 byte on-chip RAM

? On-chip XRAM

– C505/C505C : 256 byte

– C505A/C505CA : 1K byte

? 32 + 2 digital I/O lines

– Four 8-bit digital I/O ports

– One 2-bit digital I/O port (port 4)

– Port 1 with mixed analog/digital I/O capability

? Three 16-bit timers/counters

– Timer 0 / 1 (C501 compatible)

– Timer 2 with 4 channels for 16-bit capture/compare operation

? Full duplex serial interface with programmable baudrate generator (USART)

? Full CAN Module, version 2.0 B compliant (C505C and C505CA only)

– 256 register/data bytes located in external data memory area

– 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz

– internal CAN clock prescaler when input frequency is over 10 MHz

? On-chip A/D Converter

– up to 8 analog inputs

– C505/C505C : 8-bit resolution

– C505A/C505CA: 10-bit resolution

? Twelve interrupt sources with four priority levels

? On-chip emulation support logic (Enhanced Hooks Technology TM)

? Programmable 15-bit watchdog timer

? Oscillator watchdog

? Fast power on reset

? Power Saving Modes

– Slow-down mode

– Idle mode (can be combined with slow-down mode)

– Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin

? P-MQFP-44 package

? Pin configuration is compatible to C501, C504, C511/C513-family

? Temperature ranges:

SAB-C505 versions TA = 0 to 70 °C

SAF-C505 versions TA = -40 to 85°C

SAH-C505 versions TA = -40 to 110°C

SAK-C505 versions TA = -40 to 125°C