CS5571-ISZ集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書(shū)PDF中文資料

CS5571-ISZ屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由凌云邏輯制造生產(chǎn)的CS5571-ISZ模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對(duì)模擬信號(hào)進(jìn)行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號(hào)。一般來(lái)說(shuō)，數(shù)字輸出是二進(jìn)制補(bǔ)碼二進(jìn)制數(shù)，與輸入成比例。輸入類(lèi)型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線(xiàn)、SAR、三角積分、兩步式）進(jìn)行選擇。

General Description

The CS5571 is a single-channel, 16-bit analog-to-digital converter capable of 100 kSps conversion rate. The input accepts a single-ended analog input signal. On-chip buffers provide high input impedance for both the AIN input and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. The CS5571 is a delta-sigma converter capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-latency digital filter architecture.

Features

? Single-ended Analog Input

? On-chip Buffers for High Input Impedance

? Conversion Time = 10 μS

? Settles in One Conversion

? Linearity Error = 0.0008

? Signal-to-Noise = 92 dB

? S/(N + D) = 91 dB

? DNL = ±0.1 LSB Max.

? Simple three/four-wire serial interface

? Power Supply Configurations:

- Analog: +5V/GND; IO: +1.8V to +3.3V

- Analog: ±2.5V; IO: +1.8V to +3.3V

? Power Consumption:

- ADC Input Buffers On: 85 mW

- ADC Input Buffers Off: 60 mW