HYB514256B-70中文資料西門子數(shù)據(jù)手冊PDF規(guī)格書

The HYB 514256B/BJ/BL/BJL is the new generation dynamic RAM organized as 262 144 words by 4-bit. The HYB 514256B/BJ/BL/BJL utilizes CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514256B/BJ/BL/BJL to be packaged in a standard plastic P-DIP-20-2,or plastic P-SOJ-26/20-1. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 ) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. These HYB 514256BL/BJL are specially selected for battery backup applications.

Advanced Information

? 262 144 words by 4-bit organization

? Fast access and cycle time

50 ns access time

95 ns cycle time (-50 version)

60 ns access time

110 ns cycle time (-60 version)

70 ns access time

130 ns cycle time (-70 version)

? Fast page mode cycle time

35 ns (-50 version)

40 ns (-60 version)

45 ns (-70 version)

? Low power dissipation

max. 495 mW active (-50 version)

max. 440 mW active (-60 version)

max. 385 mW active (-70 version)

max. 5.5 mW standby

max. 1.1 mW standby for L-version

? Single + 5 V (± 10 ) supply with a built-in VBB generator

? Output unlatched at cycle end allows two dimensional chip selection

? Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability

? All inputs, outputs and clocks

TTL-compatible

? 512 refresh cycles/8 ms

512 refresh cycles/64 ms for L-version only

? Plastic Packages: P-DIP-20-2, P-SOJ-26/20-1