WM9714CLGEFL/V集成電路（IC）的編解碼器規(guī)格書(shū)PDF中文資料

WM9714CLGEFL/V屬于集成電路（IC）的編解碼器。由凌云邏輯制造生產(chǎn)的WM9714CLGEFL/V編解碼器編解碼器是用于通過(guò)壓縮和解壓縮來(lái)轉(zhuǎn)換數(shù)據(jù)的半導(dǎo)體器件。數(shù)據(jù)壓縮可提高傳輸速度并減少存儲(chǔ)空間。某些編解碼器提供高達(dá) 32 位的分辨率，并且分別提供多達(dá) 6 個(gè)或 8 個(gè)模數(shù)轉(zhuǎn)換器和數(shù)模轉(zhuǎn)換器。除三角積分調(diào)制外，還有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 數(shù)據(jù)接口。

DESCRIPTION

The WM9714L is a highly integrated input/output device

designed for mobile computing and communications.

The chip is architected for dual CODEC operation, supporting hifi stereo CODEC functions via the AC link interface, and

additionally supporting voice CODEC functions via a PCM type

Synchronous Serial Port (SSP). A third, auxiliary DAC is

provided which may be used to support generation of

supervisory tones, or ring-tones at different sample rates to the

main CODEC.

The device can connect directly to mono or stereo microphones,

stereo headphones and a stereo speaker, reducing total

component count in the system. Cap-less connections to the

headphones, speakers, and earpiece may be used, saving cost

and board area. Additionally, multiple analogue input and output

pins are provided for seamless integration with analogue

connected wireless communication devices.

All device functions are accessed and controlled through a

single AC-Link interface compliant with the AC’97 standard. The

24.576 MHz master clock can be input directly or generated

internally from a 13MHz (or other frequency) clock by an on-chip

PLL. The PLL supports a wide range of input clock from

2.048MHz to 78.6MHz.

The WM9714L operates at supply voltages from 1.8V to 3.6V.

Each section of the chip can be powered down under software

control to save power. The device is available in a small

leadless 7x7mm QFN package, ideal for use in hand-held

portable systems.

FEATURES

? AC’97 Rev 2.2 compatible stereo CODEC

- DAC SNR 94dB, THD –85dB

- ADC SNR 87dB, THD –86dB

- Variable Rate Audio, supports all WinCE sample rates

- Tone Control, Bass Boost and 3D Enhancement

? On-chip 45mW headphone driver

? On-chip 400mW mono or stereo speaker drivers

? Stereo, mono or differential microphone input

- Automatic Level Control (ALC)

- Mic insert and mic button press detection

? Auxiliary mono DAC (ring tone or DC level generation)

? Seamless interface to wireless chipset

? Additional PCM/I2S interface to support voice CODEC

? PLL derived audio clocks.

? Supports input clock ranging from 2.048MHz to 78.6MHz

? 1.8V to 3.6V supplies (digital down to 1.62V, speaker up to

4.2V)

? 7x7mm 48-lead QFN package

APPLICATIONS

? Smartphones

? Personal Digital Assistants (PDA)

? Handheld and Tablet Computers