24C256中文資料SYC數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? Low Voltage and Standard Voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 3.6V)

? Internally Organized 16,384 x 8 and 32,768 x 8

? 2-Wire Serial Interface

? Schmitt Trigger, Filtered Inputs for Noise Suppression

? Bidirectional Data Transfer Protocol

? 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

? Write Protect Pin for Hardware and Software Data Protection

? 64-Byte Page Write Mode (Partial Page Writes Allowed)

? Self-Timed Write Cycle (5 ms typical)

? High Reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 40 Years

– ESD Protection: > 4000V

? Automotive Grade and Extended Temperature Devices Available

? 8-Pin JEDEC PDIP, 8-Pin JEDEC and EIAJ SOIC, 14-Pin TSSOP, and

8-Pin Leadless Array Packages

Description

The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and

programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8

bits each. The device’s cascadable feature allows up to 4 devices to share a common

2-wire bus. The device is optimized for use in many industrial and commercial applications

where low power and low voltage operation are essential. The devices are available

in space-saving 8-pin JEDEC PDIP, 8-pin EIAJ, 8-pin JEDEC SOIC, 14-pin

TSSOP, and 8-pin LAP packages. In addition, the entire family is available in 5.0V

(4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.