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3D3323-50中文資料DATADELAY數(shù)據(jù)手冊(cè)PDF規(guī)格書

3D3323-50
廠商型號(hào)

3D3323-50

功能描述

MONOLITHIC TRIPLE FIXED DELAY LINE

文件大小

241.95 Kbytes

頁(yè)面數(shù)量

4 頁(yè)

生產(chǎn)廠商 Data Delay Devices, Inc.
企業(yè)簡(jiǎn)稱

DATADELAY

中文名稱

Data Delay Devices, Inc.官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2024-11-18 11:10:00

3D3323-50規(guī)格書詳情

FUNCTIONAL DESCRIPTION

The 3D3323 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains three matched, independent delay lines. Delay values can range from 10ns through 6000ns. The input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. The 3D3323 is CMOS-compatible and features both rising- and falling-edge accuracy.

FEATURES

? All-silicon, low-power CMOS technology

? Vapor phase, IR and wave solderable

? Auto-insertable (DIP pkg.)

? Low ground bounce noise

? Leading- and trailing-edge accuracy

? Delay range: 10 through 6000ns

? Delay tolerance: 2 or 1.0ns

? Temperature stability: ±3 typ (-40C to 85C)

? Vdd stability: ±1 typical (3.0V to 3.6V)

? Minimum input pulse width: 20 of total delay

? 14-pin DIP available as drop-in replacement for

? hybrid delay lines

產(chǎn)品屬性

  • 型號(hào):

    3D3323-50

  • 制造商:

    DATADELAY

  • 制造商全稱:

    Data Delay Devices, Inc.

  • 功能描述:

    MONOLITHIC TRIPLE FIXED DELAY LINE

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