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3D7205K-25中文資料DATADELAY數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

3D7205K-25
廠(chǎng)商型號(hào)

3D7205K-25

功能描述

MONOLITHIC 5-TAP FIXED DELAY LINE

文件大小

256.26 Kbytes

頁(yè)面數(shù)量

4 頁(yè)

生產(chǎn)廠(chǎng)商 Data Delay Devices, Inc.
企業(yè)簡(jiǎn)稱(chēng)

DATADELAY

中文名稱(chēng)

Data Delay Devices, Inc.官網(wǎng)

原廠(chǎng)標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2024-11-18 18:24:00

3D7205K-25規(guī)格書(shū)詳情

FUNCTIONAL DESCRIPTION

The 3D7205 5-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 8.0ns through 100ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7205 is TTL- and CMOScompatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.

FEATURES

? All-silicon, low-power CMOS technology

? TTL/CMOS compatible inputs and outputs

? Vapor phase, IR and wave solderable

? Auto-insertable (DIP pkg.)

? Low ground bounce noise

? Leading- and trailing-edge accuracy

? Delay range: 8 through 500ns

? Delay tolerance: 5 or 2ns

? Temperature stability: ±3 typical (0C-70C)

? Vdd stability: ±2 typical (4.75V-5.25V)

? Minimum input pulse width: 20 of total delay

? 14-pin DIP and 16-pin SOIC available as drop-in replacements for hybrid delay lines

產(chǎn)品屬性

  • 型號(hào):

    3D7205K-25

  • 制造商:

    DATADELAY

  • 制造商全稱(chēng):

    Data Delay Devices, Inc.

  • 功能描述:

    MONOLITHIC 5-TAP FIXED DELAY LINE

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