527R-03LF中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? Packaged as 28 pin SSOP, Pb free (150 mil body)

? Synchronizes fractional clocks rising edges

? CMOS in to PECL out

? Pin selectable dividers

? Zero input to output skew

? User determines the output frequency - no software

needed

? Slices frequency or period

? Input clock frequency of 1.5 MHz to 200 MHz

? Output clock frequencies from 2.5 MHz to 160 MHz

? Very low jitter

? Duty cycle of 45/55

? Operating voltage of 3.3 V

? Advanced, low power CMOS process