54HC595中文資料SS數(shù)據(jù)手冊PDF規(guī)格書

Description

The 74HC595 is an 8–bit serial-in to parallel-out shift

register which drives an 8–bit D–type latch with 3–state

outputs. Both register and latch have independent

positive triggered clock inputs. All registers capture

data on rising edge and change output on the falling

edge. If both clocks are connected together the input

shift register is always one clock cycle ahead of the

output register. The shift register also features

asynchronous reset. Device inputs are compatible with

standard CMOS outputs; with pull-up resistors, they are

compatible with LSTTL outputs.

Features:

Output Drive Capability: 15 LSTTL Loads

Low Input Current: 1μA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

CMOS High Noise Immunity

Function compatible with 74LS595.