56855中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

56855 General Description

? 120 MIPS at 120MHz

? 24K x 16-bit Program SRAM

? 24K x 16-bit Data SRAM

? 1K x 16-bit Boot ROM

? Access up to 2M words of program memory or 8M

words of data memory

? Chip Select Logic for glueless interface to ROM and

SRAM

? Six (6) independent channels of DMA

? Enhanced Synchronous Serial Interface (ESSI)

? Two (2) Serial Communication Interfaces (SCI)

? General Purpose 16-bit Quad Timer with 1 external pin

? JTAG/Enhanced On-Chip Emulation (OnCE?) for

unobtrusive, real-time debugging

? Computer Operating Properly (COP)/Watchdog Timer

? Time-of-Day (TOD)

? 100 LQFP package

? Up to 18 GPIO

1.1 56855 Features

1.1.1 Core

? Efficient 16-bit engine with dual Harvard architecture

? 120 Million Instructions Per Second (MIPS) at 120MHz core frequency

? Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

? Four (4) 36-bit accumulators including extension bits

? 16-bit bidirectional shifter

? Parallel instruction set with unique DSP addressing modes

? Hardware DO and REP loops

? Three (3) internal address buses and one (1) external address bus

? Four (4) internal data buses and one (1) external data bus

? Instruction set supports both DSP and controller functions

? Four (4) hardware interrupt levels

? Five (5) software interrupt levels

? Controller-style addressing modes and instructions for compact code

? Efficient C Compiler and local variable support

? Software subroutine and interrupt stack with depth limited only by memory

? JTAG/Enhanced OnCE debug programming interface

1.1.2 Memory

? Harvard architecture permits up to three (3) simultaneous accesses to program and data memory

? On-Chip Memory

— 24K × 16-bit Program SRAM

— 24K × 16-bit Data SRAM

— 1K × 16-bit Boot ROM

? Off-Chip Memory Expansion (EMI)

— Access up to 2M words of program memory or 8M words of data memory

— Chip Select Logic for glue-less interface to ROM and SRAM

1.1.3 Peripheral Circuits for 56855

? General Purpose 16-bit Quad Timer with 1 external pin*

? Two (2) Serial Communication Interfaces (SCI)*

? Enhanced Synchronous Serial Interface (ESSI) module*

? Computer Operating Properly (COP)/Watchdog Timer

? JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

? Six (6) independent channels of DMA

? Time-of-Day (TOD)

? Up to 18 GPIO

* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4 Energy Information

? Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

? Wait and Stop modes available