56F803_V01中文資料飛思卡爾數(shù)據(jù)手冊PDF規(guī)格書

56F803 General Description

? Up to 40 MIPS at 80MHz core frequency

? DSP and MCU functionality in a unified,

C-efficient architecture

? Hardware DO and REP loops

? MCU-friendly instruction set supports both DSP and

controller functions: MAC, bit manipulation unit, 14

addressing modes

? 31.5K × 16-bit words (64KB) Program Flash

? 512 × 16-bit words (1KB) Program RAM

? 4K × 16-bit words (8KB) Data Flash

? 2K × 16-bit words (4KB) Data RAM

? 2K × 16-bit words (4KB) Boot Flash

? Up to 64K × 16-bit words each of external Program

and Data memory

? 6-channel PWM module

? Two 4-channel 12-bit ADCs

? Quadrature Decoder

? CAN 2.0 B module

? Serial Communication Interface (SCI)

? Serial Peripheral Interface (SPI)

? Up to two General Purpose Quad Timers

? JTAG/OnCETM port for debugging

? 16 shared GPIO lines

? 100–pin LQFP package