56F8355中文資料飛思卡爾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

56F8355/56F8155 General Description

? Up to 60 MIPS at 60MHz core frequency

? DSP and MCU functionality in a unified, C-efficient architecture

? 256KB Program Flash

? 4KB Program RAM

? 8KB Data Flash

? 16KB Data RAM

? 16KB Boot Flash

? Up to two 6-channel PWM modules

? Four 4-channel, 12-bit ADCs

? Temperature Sensor

? Up to two Quadrature Decoders

? FlexCAN module

? Two Serial Communication Interfaces (SCIs)

? Up to two Serial Peripheral Interface (SPIs)

? Up to four general purpose Quad Timers

? Computer Operating Properly (COP)/Watchdog

? JTAG/Enhanced On-Chip Emulation (OnCE?) for unobtrusive, real-time debugging

? Up to 49 GPIO lines

? 128-pin LQFP Package

56F8355/56F8155 Features

Core

? Efficient 16-bit 56800E family controller engine with dual Harvard architecture

? Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

? Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

? Four 36-bit accumulators, including extension bits

? Arithmetic and logic multi-bit shifter

? Parallel instruction set with unique DSP addressing modes

? Hardware DO and REP loops

? Three internal address buses

? Four internal data buses

? Instruction set supports both DSP and controller functions

? Controller-style addressing modes and instructions for compact code

? Efficient C compiler and local variable support

? Software subroutine and interrupt stack with depth limited only by memory

? JTAG/EOnCE debug programming interface