5M40ZE64I5N集成電路（IC）的CPLD（復(fù)雜可編程邏輯器件）規(guī)格書PDF中文資料

Feature Summary

The following list summarizes the MAX V device family features:

■ Low-cost, low-power, and non-volatile CPLD architecture

■ Instant-on (0.5 ms or less) configuration time

■ Standby current as low as 25 μA and fast power-down/reset operation

■ Fast propagation delay and clock-to-output times

■ Internal oscillator

■ Emulated RSDS output support with a data rate of up to 200 Mbps

■ Emulated LVDS output support with a data rate of up to 304 Mbps

■ Four global clocks with two clocks available per logic array block (LAB)

■ User flash memory block up to 8 Kbits for non-volatile storage with up to 1000

read/write cycles

■ Single 1.8-V external supply for device core

■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels

■ Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

■ Schmitt triggers enabling noise tolerant inputs (programmable per pin)

■ I/Os are fully compliant with the PCI-SIG? PCI Local Bus Specification, revision

2.2 for 3.3-V operation

■ Hot-socket compliant

■ Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990

Table 1–1 lists the MAX V family features.