5P49V5913BDDDNLGI8中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

Description

The 5P49V5913 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

Programmable (OTP) memory or changed using I2C

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock? 5).

The frequencies are generated from a single reference clock.

The reference clock can come from one of the two redundant

clock inputs. A glitchless manual switchover function allows

one of the redundant clocks to be selected during normal

operation.

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

The device may be configured to use one of two I2C

addresses to allow multiple devices to be used in a system.

Features

? Generates up to two independent output frequencies

? High performance, low phase noise PLL, < 0.7ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1GbE and 10GbE

? Two fractional output dividers (FODs)

? Independent Spread Spectrum capability on each output

pair

? Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

? I

2C serial programming interface

? One reference LVCMOS output clock

? Two universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

? I/O Standards:

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os: LVPECL, LVDS and HCSL

? Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

– Crystal frequency range: 8MHz to 40MHz

? Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

? Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

? Redundant clock inputs with manual switchover

? Programmable loop bandwidth

? Programmable slew rate control

? Programmable crystal load capacitance

? Individual output enable/disable

? Power-down mode

? 1.8V, 2.5V or 3.3V core VDDD, VDDA

? 4 × 4 mm 24-VFQFPN package

? -40° to +85°C industrial temperature operation