5P49V5914集成電路（IC）的時鐘發(fā)生器PLL頻率合成器規(guī)格書PDF中文資料

Features

? Generates up to three independent output frequencies

? High performance, low phase noise PLL, <0.7ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1GbE and 10GbE

? Three fractional output dividers (FODs)

? Independent Spread Spectrum capability on each output

pair

? Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

? I2C serial programming interface

? One reference LVCMOS output clock

? Three universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

? I/O Standards:

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os: LVPECL, LVDS and HCSL

? Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

– Crystal frequency range: 8MHz to 40MHz

? Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

? Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

? Redundant clock inputs with manual switchover

? Programmable loop bandwidth

? Programmable slew rate control

? Programmable crystal load capacitance

? Individual output enable/disable

? Power-down mode

? 1.8V, 2.5V or 3.3V core VDDD, VDDA

? Available in 24-pin VFQFPN 4mm x 4mm package

? -40° to +85°C industrial temperature operation