FEATURES:

? Guaranteed Low Skew < 60ps (max)

? Very low duty cycle distortion

? High speed propagation delay < 2.5ns. (max)

? Up to 250MHz operation

? Very low CMOS power levels

? 1.5V VDDQ for HSTL interface

? Hot insertable and over-voltage tolerant inputs

? 3-level inputs for selectable interface

? Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input

interface

? Selectable differential or single-ended inputs and fi ve single-ended outputs

? 2.5V VDD

? Available in TSSOP package

? For new designs use functional replacement 8L30110

DESCRIPTION:

The 5T905 2.5V single data rate (SDR) clock buffer is a user-selectable

single-ended or differential input to fi ve single-ended outputs buffer built on

advanced metal CMOS technology. The SDR clock buffer fanout from a

single or differential input to fi ve single-ended outputs reduces the loading

on the preceding driver and provides an effi cient clock distribution network.

The IDT5T905 can act as a translator from a differential HSTL, eHSTL,

1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to

HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled

by 3-level input signals that may be hard-wired to appropriate high-mid-low

levels. Multiple power and grounds reduce noise.

5T905屬于集成電路（IC） > 時鐘緩沖器，驅(qū)動器。瑞薩科技有限公司制造生產(chǎn)的5T905時鐘緩沖器，驅(qū)動器時鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進行所用電信號格式轉(zhuǎn)換。