6P41505中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Description

The 6P41505 is a system clock generator intended for high

performance consumer, networking, industrial, computing,

and data-communications applications.

The frequencies are generated from a single reference clock

or crystal.

Features

? Default output clocks and frequencies:

? OUT0: 25MHz LVCMOS. VDDO0 = 3.3V.

? OUT1: 33MHz or 14.318MHz (6P41505B) LVCMOS x

2(phase aligned). VDDO1=3.3V.

? OUT2: 100MHz or 48MHz (6P41505B) LVCMOS x 2

(180° phase difference). VDDO2 = 3.3V.

? OUT3, 5–11: 100MHz PCIe Gen1/2/3 compliant

differential LP-HCSL outputs x 8. VDDO3 = 1.8V.

? OUT4: 200MHz differential LVDS. VDDO4 = 3.3V.

? High performance, low phase noise PLL, < 0.7 ps RMS

typical phase jitter on outputs:

? PCIe Gen1, 2, 3 compliant clock capability

? USB 3.0 compliant clock capability

? 1GbE and 10GbE

? Independent Spread Spectrum capability

? I

2C serial programming interface

? 25MHz crystal as input reference

? Power-down mode

? Mixed voltage operation:

? 1.8V core

? 1.8V VDDO for 8 LP-HCSL outputs

? 1.8V to 3.3V VDDO for other outputs

(3 differential outputs and 1 reference output)

? See Pin Descriptions for details

? Available in 48-VFQFPN package

? -40° to +85°C industrial temperature operation

Applications

? Ethernet switch/router

? PCI Express 1.0/2.0/3.0

? Broadcast video/audio timing

? Multi-function printer

? Processor and FPGA clocking

? Any-frequency clock conversion

? MSAN/DSLAM/PON

? Fiber Channel, SAN

? Telecom line cards

? 1GbE and 10GbE