70V7339S133BF8集成電路（IC）的存儲器規(guī)格書PDF中文資料

Features:

◆ 512K x 18 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

– 64 independent 8K x 18 banks

– 9 megabits of memory on chip

◆ Bank access controlled via bank address pins

◆ High-speed data access

– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

◆ Selectable Pipelined or Flow-Through output mode

◆ Counter enable and repeat features

◆ Dual chip enables allow for depth expansion without

additional logic

◆ Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆ Separate byte controls for multiplexed bus and bus

matching compatibility

◆ LVTTL- compatible, 3.3V (±150mV) power supply

for core

◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆ Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

◆ Available in 208-pin fine pitch Ball Grid Array (fpBGA) and

256-pin Ball Grid Array (BGA)

◆ Supports JTAG features compliant with IEEE 1149.1

◆ Green parts available, see ordering information