? Two independent FIFOs (64 X 36 storage capacity each) buffer

data between bidirectional 36-bit port A and two unidirectional

18/9-bit ports (Port B transmits, Port C receives)

? Clock frequencies up to 67 MHz (10 ns access time)

Free-running clock lines for each port: CLKA, CLKB and CLKC,

may be asynchronous or coincident (simultaneous reading and

writing of data is permitted)

? IDT Standard timing

? Empty flag functions: EFA (synchronized by CLKA) and EFB

(synchronized by CLKB)

? Full flag functions: FFA (synchronized by CLKA) and FFC

(synchronized by CLKC)

? Programmable Almost-Empty and Almost-Full flags; each has

four default offsets (4, 8, 12 and 16)

? Bus sizing of 18-bits (word) and 9-bits (byte) for ports B and C

? Byte order swapping on ports B and C

? Passive parity checking on ports A and C

? Parity generation can be selected for ports A and B

? Master Reset clears data and configures FIFO