723633L12PFG8集成電路（IC）的FIFO存儲器規(guī)格書PDF中文資料

? Memory storage capacity:

IDT723623 – 256 x 36

IDT723633 – 512 x 36

IDT723643 – 1,024 x 36

? Clocked FIFO buffering data from Port A to Port B

? Clock frequencies up to 83 MHz (8 ns access time)

? IDT Standard timing (using EF and FF) or First Word Fall

Through Timing (using OR and IR flag functions)

? Programmable Almost-Empty and Almost-Full flags; each has

three default offsets (8, 16 and 64)

? Serial or parallel programming of partial flags

? Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)

? Big- or Little-Endian format for word and byte bus sizes