首頁(yè)>72V2113L7-5PFBCG8>規(guī)格書(shū)詳情
72V2113L7-5PFBCG8中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠商型號(hào) |
72V2113L7-5PFBCG8 |
| 功能描述 | 3.3 VOLT HIGH-DENSITY SUPERSYNC II? NARROW BUS FIFO 131,072 x 18/262,144 x 9 262,144 x 18/524,288 x 9 |
| 文件大小 |
496.57 Kbytes |
| 頁(yè)面數(shù)量 |
47 頁(yè) |
| 生產(chǎn)廠商 | Renesas Technology Corp |
| 企業(yè)簡(jiǎn)稱 |
RENESAS【瑞薩】 |
| 中文名稱 | 瑞薩科技有限公司官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-1-15 8:40:00 |
72V2113L7-5PFBCG8規(guī)格書(shū)詳情
FEATURES:
? Choose among the following memory organizations:
IDT72V2103 ? 131,072 x 18/262,144 x 9
IDT72V2113 ? 262,144 x 18/524,288 x 9
? Functionally compatible with the IDT72V255LA/72V265LA and
IDT72V275/72V285 SuperSync FIFOs
? Up to 166 MHz Operation of the Clocks
? User selectable Asynchronous read and/or write ports (BGA Only)
? 6 ns read/write cycle time (4.0 ns access time)
? User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
? Big-Endian/Little-Endian user selectable byte representation
? 5V tolerant inputs
? Fixed, low first word latency
? Zero latency retransmit
? Auto power down minimizes standby power consumption
? Master Reset clears entire FIFO
? Partial Reset clears data, but retains programmable settings
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|---|---|---|---|---|---|---|---|
RENESAS(瑞薩)/IDT |
2021+ |
TQFP-80(14x14) |
499 |
詢價(jià) | |||
Integrated Device Technology |
2022+ |
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RENESAS(瑞薩)/IDT |
23+ |
TQFP80(14x14) |
7350 |
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45 |
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RENESAS(瑞薩)/IDT |
23+ |
TQFP80(14x14) |
6000 |
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Renesas |
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45 |
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RENESAS(瑞薩)/IDT |
1921+ |
TQFP-80(14x14) |
3575 |
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Renesas |
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13022 |
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80-LQFP |
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RENESAS(瑞薩電子) |
22+ |
NA |
500000 |
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詢價(jià) |
