72V235L20PFG8中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES:

? 256 x 18-bit organization array (IDT72V205)

? 512 x 18-bit organization array (IDT72V215)

? 1,024 x 18-bit organization array (IDT72V225)

? 2,048 x 18-bit organization array (IDT72V235)

? 4,096 x 18-bit organization array (IDT72V245)

? 10 ns read/write cycle time

? 5V input tolerant

? IDT Standard or First Word Fall Through timing

? Single or double register-buffered Empty and Full flags

? Easily expandable in depth and width

? Asynchronous or coincident Read and Write Clocks

? Asynchronous or synchronous programmable Almost-Empty

and Almost-Full flags with default settings

? Half-Full flag capability

? Output enable puts output data bus in high-impedance state

? High-performance submicron CMOS technology

? Available in a 64-lead thin quad flatpack (TQFP/STQFP)