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72V273L6BCGI中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

72V273L6BCGI
廠商型號(hào)

72V273L6BCGI

功能描述

3.3 VOLT HIGH-DENSITY SUPERSYNC II? NARROW BUS FIFO

文件大小

480.61 Kbytes

頁(yè)面數(shù)量

46 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2024-11-8 18:30:00

72V273L6BCGI規(guī)格書詳情

FEATURES:

? Choose among the following memory organizations:

IDT72V223 ? 512 x 18/1,024 x 9

IDT72V233 ? 1,024 x 18/2,048 x 9

IDT72V243 ? 2,048 x 18/4,096 x 9

IDT72V253 ? 4,096 x 18/8,192 x 9

IDT72V263 ? 8,192 x 18/16,384 x 9

IDT72V273 ? 16,384 x 18/32,768 x 9

IDT72V283 ? 32,768 x 18/65,536 x 9

IDT72V293 ? 65,536 x 18/131,072 x 9

? Functionally compatible with the IDT72V255LA/72V265LA and

IDT72V275/72V285 SuperSync FIFOs

? Up to 166 MHz Operation of the Clocks

? User selectable Asynchronous read and/or write ports (BGA Only)

? User selectable input and output port bus-sizing

- x9 in to x9 out

- x9 in to x18 out

- x18 in to x9 out

- x18 in to x18 out

? Pin to Pin compatible to the higher density of IDT72V2103/72V2113

? Big-Endian/Little-Endian user selectable byte representation

? 5V tolerant inputs

? Fixed, low first word latency

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