72V51256L7-5BBI中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES:

? Choose from among the following memory density options:

IDT72V51236 ? Total Available Memory = 589,824 bits

IDT72V51246 ? Total Available Memory = 1,179,648 bits

IDT72V51256 ? Total Available Memory = 2,359,296 bits

? Configurable from 1 to 4 Queues

? Queues may be configured at master reset from the pool of

Total Available Memory in blocks of 256 x 36

? Independent Read and Write access per queue

? User programmable via serial port

? Default multi-queue device configurations

-IDT72V51236: 4,096 x 36 x 4Q

-IDT72V51246: 8,192 x 36 x 4Q

-IDT72V51256: 16,384 x 36 x 4Q

? 100 Bus Utilization, Read and Write on every clock cycle

? 166 MHz High speed operation (6ns cycle time)

? 3.7ns access time

? Individual, Active queue flags (OV, FF, PAE, PAF, PR)