74ABT161543中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The 74ABT161543 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT161543 16-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (nLEAB, nLEBA) and Output Enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control of data transfer in either direction. Master reset (MR) clears all registers simultaneously and sets them Low. The outputs are guaranteed to sink 64mA.

Two options are available, 74ABT161543 which does not have the Bus hold feature and 74ABTH161543 which inorporates the Bus hold feature.

FEATURES

? Two 8-bit octal transceivers with D-type latch

? Live insertion/extraction permitted

? Power-up 3-State

? Power-up reset

? Multiple VCC and GND pins minimize switching noise

? Back-to-back registers for storage

? Separate controls for data flow in each direction

? 74ABTH161543 incorporates Bus hold data inputs which eliminate

the need for external pull-up resistors to hold unused inputs

? Output capability: +64mA/–32mA

? Latch-up protection exceeds 500mA per Jedec Std 17

? ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

? Same function as ABT16543 except for additional Master Reset

control pins