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74ABTH16899DGG中文資料飛利浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

74ABTH16899DGG
廠商型號

74ABTH16899DGG

功能描述

18-bit latched transceiver with 16-bit parity generator/checker 3-State

文件大小

105.46 Kbytes

頁面數(shù)量

16

生產(chǎn)廠商 NXP Semiconductors
企業(yè)簡稱

Philips飛利浦

中文名稱

荷蘭皇家飛利浦官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-1-13 23:00:00

74ABTH16899DGG規(guī)格書詳情

DESCRIPTION

The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

FEATURES

? Symmetrical (A and B bus functions are identical)

? Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions

? Independent transparent latches for A-to-B and B-to-A directions

? Selectable ODD/EVEN parity

? Continuously checks parity of both A bus and B bus latches as ERRA and ERRB

? Open-collector ERR output

? Ability to simultaneously generate and check parity

? Can simultaneously read/latch A and B bus data

? Output capability: +64 mA/–32mA

? Latch-up protection exceeds 500mA per Jedec Std 17

? ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

? Power up 3-State

? Power-up reset

? Live insertion/extraction permitted

? Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

產(chǎn)品屬性

  • 型號:

    74ABTH16899DGG

  • 功能描述:

    總線收發(fā)器 18-BIT LATCH XCVR W/PAR/BUS 3S

  • RoHS:

  • 制造商:

    Fairchild Semiconductor

  • 邏輯類型:

    CMOS

  • 邏輯系列:

    74VCX

  • 每芯片的通道數(shù)量:

    16

  • 輸入電平:

    CMOS

  • 輸出電平:

    CMOS

  • 輸出類型:

    3-State

  • 高電平輸出電流:

    - 24 mA

  • 低電平輸出電流:

    24 mA

  • 傳播延遲時間:

    6.2 ns

  • 電源電壓-最大:

    2.7 V, 3.6 V

  • 電源電壓-最小:

    1.65 V, 2.3 V

  • 最大工作溫度:

    + 85 C

  • 封裝/箱體:

    TSSOP-48

  • 封裝:

    Reel

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