74AC373TTR集成電路（IC）的鎖存器規(guī)格書PDF中文資料

74AC373TTR屬于集成電路（IC）的鎖存器。由意法半導體集團制造生產(chǎn)的74AC373TTR鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設備輸出在鎖存使能信號有效時反映輸入的當前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時改變。

DESCRIPTION

The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state.

This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 4μA(MAX.) at TA=25°C

■ HIGH NOISE IMMUNITY:

VNIH = VNIL = 28 VCC (MIN.)

■ 50? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 6V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373

■ IMPROVED LATCH-UP IMMUNITY