74ACT138集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

74ACT138屬于集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器。由意法半導(dǎo)體集團制造生產(chǎn)的74ACT138信號開關(guān)，多路復(fù)用器，解碼器邏輯型信號開關(guān)、多路復(fù)用器和編碼器 IC 可用于對以數(shù)字格式表示數(shù)據(jù)的電信號進行路由和選擇。這些器件與設(shè)計用于模擬信號的類似產(chǎn)品有所不同，它們保留的信息表示為兩個電狀態(tài)之一，而不是兩個外部界限內(nèi)的無窮變化量。

DESCRIPTION

The 74ACT138 is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.

If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high.

Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems.

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION:

ICC = 4μA(MAX.) at TA=25°C

■ COMPATIBLE WITH TTL OUTPUTS

VIH = 2V (MIN.), VIL = 0.8V (MAX.)

■ 50? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN)

■ BALANCED PROPAGATION DELAYS:

tPLH = tPHL

■ OPERATING VOLTAGE RANGE:

VCC (OPR) = 4.5V to 5.5V

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138

■ IMPROVED LATCH-UP IMMUNITY