74AHC257PW集成電路（IC）的信號開關(guān)多路復(fù)用器解碼器規(guī)格書PDF中文資料

1. General description

The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard

No. 7-A.

The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs,

which select 4 bits of data from two sources and are controlled by a common data select

input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and

the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data

appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.

The 74AHC257; 74AHCT257 is the logic implementation of a 4-pole 2-position switch,

where the position of the switch is determined by the logic levels applied to input S. The

outputs are forced to a high-impedance OFF-state when OE is HIGH.

The logic equations for the outputs are:

1Y = OE ′ (1I1 ′ S + 1I0 ′ S)

2Y = OE ′ (2I1 ′ S + 2I0 ′ S)

3Y = OE ′ (3I1 ′ S + 3I0 ′ S)

4Y = OE ′ (4I1 ′ S + 4I0 ′ S)

The 74AHC257; 74AHCT257 is identical to the 74AHC258; 74AHCT258, but has

non-inverting (true) outputs.

2. Features

n Balanced propagation delays

n All inputs have Schmitt-trigger actions

n Non-inverting data path

n Inputs accept voltages higher than VCC

n Input levels:

u For 74AHC257: CMOS level

u For 74AHCT257: TTL level

n ESD protection:

u HBM EIA/JESD22-A114E exceeds 2000 V

u MM EIA/JESD22-A115-A exceeds 200 V

u CDM EIA/JESD22-C101C exceeds 1000 V

n Multiple package options

n Specified from -40 °C to +85 °C and from -40 °C to +125 °C