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74AHC573D集成電路（IC）的鎖存器規(guī)格書PDF中文資料

廠商型號	74AHC573D
參數屬性	74AHC573D 封裝/外殼為20-SOIC（0.295"，7.50mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的鎖存器；產品描述：IC OCTAL D TRANSP LATCH 20SOIC
功能描述	Octal D-type transparent latch; 3-state
封裝外殼	20-SOIC（0.295"，7.50mm 寬）
文件大小	281.34 Kbytes
頁面數量	16 頁
生產廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網
原廠標識
數據手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-30 14:36:00

1. General description

The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device

features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs

enter the latches. In this condition the latches are transparent, a latch output will change each time

its corresponding D-input changes. When LE is LOW the latches store the information that was

present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE

causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not

affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these

devices as translators in mixed voltage environments.

2. Features and benefits

? Wide supply voltage range from 2.0 V to 5.5 V

? Balanced propagation delays

? All inputs have Schmitt-trigger action

? Overvoltage tolerant inputs to 5.5 V

? High noise immunity

? CMOS low power dissipation

? Common 3-state output enable input

? Functionally identical to the 74AHC373; 74AHCT373

? Input levels:

? For 74AHC573: CMOS input level

? For 74AHCT573: TTL input level

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C