1. General description

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with

Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs

and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all

flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced

LOW, independent of clock or data inputs, by a LOW on the MR input.

The device is useful for applications where only the true output is required and the clock and

master reset are common to all storage elements.

2. Features

? Balanced propagation delays

? All inputs have Schmitt-trigger actions

? Inputs accept voltages higher than VCC

? Ideal buffer for MOS microcontroller or memory

? Common clock and master reset

? Input levels:

? For 74AHC273: CMOS level

? For 74AHCT273: TTL level

? ESD protection:

? HBM JESD22-A114E exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101C exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74AHCT273D屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國(guó))有限公司制造生產(chǎn)的74AHCT273D觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。