74AHCT377D集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

廠商型號	74AHCT377D
參數(shù)屬性	74AHCT377D 封裝/外殼為20-SOIC（0.295"，7.50mm 寬）；包裝為卷帶（TR）；類別為集成電路（IC）的觸發(fā)器；產(chǎn)品描述：IC FF D-TYPE SNGL 8BIT 20SO
功能描述	Octal D-type flip-flop with data enable; positive-edge trigger
文件大小	601.79 Kbytes
頁面數(shù)量	16 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-1 14:16:00

1. General description

The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard

No. 7-A.

The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D

inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when

the data enable input (E) is LOW. The state of each D input, one set-up time before the

LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the

flip-flop. The E input is only required to be stable one set-up time prior to the

LOW-to-HIGH transition for predictable operation.

For versions associated with the 74AHC377; 74AHCT377, refer to the following:

? For the master reset version, see 74AHC273; 74AHCT273

? For the transparent latch version, see 74AHC373; 74AHCT373

? For the 3-state version, see 74AHC374; 74AHCT374

2. Features

n Balanced propagation delays

n All inputs have Schmitt-trigger actions

n Inputs accept voltages higher than VCC

n Ideal for addressable register applications

n Data enable for address and data synchronization

n Eight positive-edge triggered D-type flip-flops

n Input levels:

u For 74AHC377: CMOS level

u For 74AHCT377: TTL level

n ESD protection:

u HBM EIA/JESD22-A114E exceeds 2000 V

u MM EIA/JESD22-A115-A exceeds 200 V

u CDM EIA/JESD22-C101C exceeds 1000 V

n Multiple package options

n Specified from -40 °C to +85 °C and from -40 °C to +125 °C