74AHCT74PW集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

廠商型號	74AHCT74PW
參數(shù)屬性	74AHCT74PW 封裝/外殼為14-TSSOP（0.173"，4.40mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的觸發(fā)器；產(chǎn)品描述：IC FF D-TYPE DUAL 1BIT 14TSSOP
功能描述	Dual D-type flip-flop with set and reset; positive-edge trigger
封裝外殼	14-TSSOP（0.173"，4.40mm 寬）
文件大小	256.18 Kbytes
頁面數(shù)量	15 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-1-19 23:00:00

1. General description

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with

Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data

inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary

outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock

input. Information on the data input is transferred to the Q output on the LOW to HIGH transition

of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock

transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall

times.

2. Features and benefits

? Balanced propagation delays

? All inputs have Schmitt-trigger actions

? Inputs accept voltages higher than VCC

? Input levels:

? For 74AHC74: CMOS level

? For 74AHCT74: TTL level

? ESD protection:

? HBM EIA/JESD22-A114E exceeds 2000 V

? MM EIA/JESD22-A115-A exceeds 200 V

? CDM EIA/JESD22-C101C exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C