74ALVC162334A集成電路（IC）的通用總線功能規(guī)格書(shū)PDF中文資料

1. General description

The 74ALVC162334A is a 16-bit universal bus driver. Data flow is controlled by

active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP).

When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at

LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is

stored in the latch/flip-flop.

The 74ALVC162334A is designed with 30 W series resistors in both HIGH or LOW output

stages.

When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the

high-impedance OFF-state. Operation of the OE input does not affect the state of the

latch/flip-flop.

To ensure the high-impedance state during power-up or power-down, OE should be tied to

VCC through a pull-up resistor; the minimum value of the resistor is determined by the

current-sinking capability of the driver.

2. Features

n Wide supply voltage range of 1.2 V to 3.6 V

n Complies with JEDEC standard 8-1A

n CMOS low power consumption

n Direct interface with TTL levels

n Current drive: ±24 mA at 3.0 V

n MULTIBYTE flow-through standard pinout architecture

n Low inductance multiple VCC and GND pins for minimum noise and ground bounce

n Output drive capability 50 W transmission lines at 85 °C

n Integrated 30 W termination resistors

n Input diodes to accommodate strong drivers