74ALVC16245DGG集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

1. General description

The 74ALVC16245; 74ALVCH16245 is a 16-bit transceiver with 3-state outputs. The device can be

used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables

(1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for

direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. This

device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables

the output, preventing the potentially damaging backflow current through the device when it is

powered down.

The 74ALVCH16245 has an active bushold circuitry which is provided to hold unused or floating

data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down

resistors.

2. Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power consumption

? MULTIBYTE flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimize noise and ground bounce

? Overvoltage tolerant inputs to 5.5 V

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? All data inputs have bushold (74ALVCH16245 only)

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Output drive capability 50 Ω transmission lines at 85 °C

? Current drive ±24 mA at VCC = 3.0 V.

? Complies with JEDEC standards:

? JESD8-5 (2.3 V to 2.7 V)

? JESD8B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

? CDM JESD22-C101E exceeds 1000 V