74ALVC162834A集成電路（IC）的通用總線功能規(guī)格書PDF中文資料

廠商型號	74ALVC162834A
參數(shù)屬性	74ALVC162834A 封裝/外殼為56-TFSOP（0.240"，6.10mm 寬）；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的通用總線功能；產(chǎn)品描述：IC UNIV BUS DVR 18BIT 56TSSOP
功能描述	18-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state
封裝外殼	56-TFSOP（0.240"，6.10mm 寬）
文件大小	202.15 Kbytes
頁面數(shù)量	15 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-5-29 23:00:00
人工找貨	74ALVC162834A價格和庫存，歡迎聯(lián)系客服免費人工找貨

1 General description

The 74ALVC162834A is an 18-bit registered driver. Data flow is controlled by active low

output enable (OE), active low latch enable (LE) and clock inputs (CP).

When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held

at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is

stored in the latch/flip-flop.

The 74ALVC162834A is designed with 30 Ω series resistors in both HIGH or LOW output

stages.

When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high

impedance OFF-state. Operation of the OE input does not affect the state of the latch/

flip-flop.

To ensure the high-impedance state during power up or power down, OE should be tied

to VCC through a pull-up resistor; the minimum value of the resistor is determined by the

current-sinking capability of the driver.

2 Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low-power consumption

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Current drive ± 12 mA at 3.0 V

? MULTIBYTE flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimum noise and ground bounce

? Output drive capability 50 Ω transmission lines at 85°C

? Integrated 30 Ω termination resistors

? Diode clamps to VCC and GND on all inputs

? Input diodes to accommodate strong drivers

? Complies with JEDEC standard no. 8-1A