74ALVC162836A集成電路（IC）的通用總線功能規(guī)格書PDF中文資料

1 General description

The 74ALVC162836A is a 20-bit universal bus driver. Data flow is controlled by output

enable (OE), latch enable (LE) and clock inputs (CP).

When LE is HIGH, the An to Yn data flow is transparent. When LE is HIGH and CP is

held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the Adata

is stored in the latch/flip-flop.

The 74ALVC162836A is designed with 30 Ω series resistors in both HIGH or LOW output

stages.

When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the

high impedance OFF-state. Operation of the OE input does not affect the state of the

latch/flip-flop.

To ensure the high-impedance state during power up or power down, OE should be tied

to VCC through a pullup resistor; the minimum value of the resistor is determined by the

current-sinking capability of the driver.

2 Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low-power consumption

? Direct interface with TTL levels

? Current drive ± 12 mA at 3.0 V

? MULTIBYTE flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimum noise and ground bounce

? Output drive capability 50 Ω transmission lines at 85°C

? Integrated 30 Ω termination resistors

? Diode clamps to VCC and GND on all inputs

? Input diodes to accommodate strong drivers

? Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V