74ALVC373PW集成電路（IC）的鎖存器規(guī)格書PDF中文資料

1. General description

The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch

enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches.

In this condition the latches are transparent, a latch output will change each time its corresponding

D-input changes. When LE is LOW the latches store the information that was present at the inputs

a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs

to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of

the latches. This device is fully specified for partial power down applications using IOFF. The IOFF

circuitry disables the output, preventing the potentially damaging backflow current through the

device when it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 3.6 V

? 3.6 V tolerant inputs/outputs

? CMOS low power consumption

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Power-down mode

? Latch-up performance exceeds 250 mA

? Complies with JEDEC standards:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8B (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114E exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from -40 °C to +85 °C