74ALVCH16240集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書(shū)PDF中文資料

General Description

The ALVCH16240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.

The ALVCH16240 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating inputs at a valid logic level.

The 74ALVCH16240 is designed for low voltage (1.65V to 3.6V) VCC applications with output capability up to 3.6V.

The 74ALVCH16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain ing low CMOS power dissipation.

Features

■ 1.65V to 3.6V VCC supply operation

■ 3.6V tolerant control inputs and outputs

■ Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

■ tPD

3.9 ns max for 3.0V to 3.6V VCC

5.3 ns max for 2.3V to 2.7V VCC

6.0 ns max for 1.65V to 1.95V VCC

■ Uses patented noise/EMI reduction circuitry

■ Latch-up conforms to JEDEC JED78

■ ESD performance:

Human body model > 2000V

Machine model > 200V