74ALVCH16373DT集成電路（IC）的鎖存器規(guī)格書(shū)PDF中文資料

74ALVCH16373DT屬于集成電路（IC）的鎖存器。由安森美半導(dǎo)體公司制造生產(chǎn)的74ALVCH16373DT鎖存器鎖存器是類(lèi)似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類(lèi)似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變。“透明”鎖存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

Low-Voltage 16-Bit Transparent Latch with Bus Hold 1.8/2.5/3.3 V (3–State, Non–Inverting)

The 74ALVCH16373 is an advanced performance, non–inverting 16–bit transparent latch. It is designed for very high–speed, very low–power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16373 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16–bit operation.

The 74ALVCH16373 contains 16 D–type latches with 3–state 3.6 V–tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, (a latch output will change state each time its D input changes). When LE is LOW, the latch stores the information that was present on the D inputs a setup time preceding the HIGH–to–LOW transition of LE. The 3–state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. The data inputs include active bushold circuitry, eliminating the need for external pull–up resistors to hold unused or floating inputs at a valid logic state.

? Designed for Low Voltage Operation: VCC = 1.65 – 3.6 V

? 3.6 V Tolerant Inputs and Outputs

? High Speed Operation:

3.0 ns max for 3.0 to 3.6 V

3.9 ns max for 2.3 to 2.7 V

6.8 ns max for 1.65 to 1.95 V

? Static Drive:

±24 mA Drive at 3.0 V

±18 mA Drive at 2.3 V

±6 mA Drive at 1.65 V

? Supports Live Insertion and Withdrawal

? Includes Active Bushold to Hold Unused or Floating Inputs at a Valid

Logic State

? IOFF Specification Guarantees High Impedance When VCC = 0 V?

? Near Zero Static Supply Current in All Three Logic States (20 μA)

Substantially Reduces System Power Requirements

? Latchup Performance Exceeds ±250 mA @ 125°C

? ESD Performance:

Human Body Model >2000 V;

Machine Model >200 V

? Second Source to Industry Standard 74ALVCH16373