1 General description

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs

for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold

data inputs which eliminate the need for external pull-up resistors to hold unused inputs.

The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock

(nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clockenable

(nCE) input are provided for each total 9-bit section.

With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of

their individual nDn-inputs that meet the set-up and hold time requirements on the

LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching

the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go

LOW independently of the clock.

When nOE is LOW, the contents of the flip-flops are available at the outputs. When the

nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE

input does not affect the state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic

level.

2 Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low-power consumption

? Direct interface with TTL levels

? Current drive ± 24 mA at 3.0 V

? MULTIBYTE flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimum noise and ground bounce

? Output drive capability 50 Ω transmission lines at 85°C

? All data inputs have bushold

? Complies with JEDEC standard no. 8-1A

? Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V

74ALVCH16823DGG屬于集成電路（IC） > 觸發(fā)器。安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74ALVCH16823DGG觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。