74ALVCH16825DGG集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

1 General description

The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with 3-state outputs for

bus-oriented applications.

The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals.

For either 9-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1

and 2OE2) inputs must both be LOW for corresponding nYn outputs to be active. If

either output enable input is HIGH, the outputs of that 9-buffer section are in the high

impedance state.

The 74ALVCH16825 has active bus hold circuitry which is provided to hold unused or

floating data inputs at a valid logic level. This feature eliminates the need for external

pull-up or pull-down resistors.

2 Features and benefits

? Wide supply voltage range of 1.2V to 3.6V

? CMOS low power consumption

? MultiByte flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimum noise and ground bounce

? Direct interface with TTL levels (2.7 V to 3.6 V)

? Bus hold on data inputs

? Output drive capability 50 Ω transmission lines at 85 °C

? Current drive ±24 mA at 3.0 V

? Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V