74ALVCH16843DGG集成電路（IC）的鎖存器規(guī)格書PDF中文資料

1 General description

The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each

latch and 3-State outputs for bus oriented applications. The two sections of each register

are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and

output enable (nOE) control gates.

When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH,

the outputs are in the high impedance OFF state. Operation of the nOE input does not

affect the state of the flip-flops.

The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or

floating data inputs at a valid logic level. This feature eliminates the need for external

pull-up or pull-down resistors.

2 Features and benefits

? Wide supply voltage range of 1.2V to 3.6V

? CMOS low power consumption

? Direct interface with TTL levels

? Current drive ±24 mA at VCC = 3.0 V.

? MULTIBYTE flow-through standard pin-out architecture

? Low inductance multiple VCC and GND pins for minimize noise and ground bounce

? All data inputs have bushold

? Output drive capability 50 Ω transmission lines at 85 °C

? 3-state non-inverting outputs for bus oriented applications

? Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

? ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V