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74ALVCH16952DGG中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書
74ALVCH16952DGG規(guī)格書詳情
DESCRIPTION
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bi-directional busses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPXX, where X is AB or BA) provided that the clock enable (CEXX) is LOW. The data is then present at the 3-State output buffers, but is only accessible when the output enable input (OEXX) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.
FEATURES
? Complies with JEDEC standard no. 8-1A
? CMOS low power consumption
? MULTIBYTETM flow-through pin-out architecture
? Low inductance, multiple center power and ground pins for
minimum noise and ground bounce
? Direct interface with TTL levels
? Output drive capability 50? transmission lines @ 85°C
產(chǎn)品屬性
- 型號：
74ALVCH16952DGG
- 功能描述：
總線收發(fā)器 16-BIT REG. TRANSCVR
- RoHS：
否
- 制造商：
Fairchild Semiconductor
- 邏輯類型：
CMOS
- 邏輯系列：
74VCX
- 每芯片的通道數(shù)量：
16
- 輸入電平：
CMOS
- 輸出電平：
CMOS
- 輸出類型：
3-State
- 高電平輸出電流：
- 24 mA
- 低電平輸出電流：
24 mA
- 傳播延遲時間：
6.2 ns
- 電源電壓-最大：
2.7 V, 3.6 V
- 電源電壓-最?。?/span>
1.65 V, 2.3 V
- 最大工作溫度：
+ 85 C
- 封裝/箱體：
TSSOP-48
- 封裝：
Reel
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
恩XP |
22+ |
56TSSOP |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價 | ||
PHI |
24+ |
TSSOP |
3500 |
原裝現(xiàn)貨,可開13%稅票 |
詢價 | ||
PHI |
2023+ |
TSSOP |
50000 |
原裝現(xiàn)貨 |
詢價 | ||
恩XP |
24+ |
TSSOP-20 |
30000 |
原裝正品公司現(xiàn)貨,假一賠十! |
詢價 | ||
PHI |
22+ |
TSSOP |
8000 |
原裝正品支持實單 |
詢價 | ||
恩XP |
22+ |
NA |
45000 |
加我QQ或微信咨詢更多詳細信息, |
詢價 | ||
24+ |
N/A |
64000 |
一級代理-主營優(yōu)勢-實惠價格-不悔選擇 |
詢價 | |||
Nexperia USA Inc. |
24+ |
56-TSSOP |
65200 |
一級代理/放心采購 |
詢價 | ||
恩XP |
25+ |
TSSOP-20 |
8880 |
原裝認準(zhǔn)芯澤盛世！ |
詢價 | ||
恩XP |
21+ |
TSSOP-20 |
8080 |
只做原裝,質(zhì)量保證 |
詢價 |
