74ALVCH16952DGG集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書PDF中文資料

1 General description

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting

registered transceiver. Two 8-bit back to back registers store data flowing in both

directions between two bidirectional buses. Data applied to the inputs is entered and

stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock

enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but

is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow

from A inputs to B outputs is the same as for B inputs to A outputs.

2 Features and benefits

? CMOS low-power consumption

? Multibyte flow-through pinout architecture

? Low inductance, multiple center power and ground pins for minimum noise and ground

bounce

? Direct interface with TTL levels

? Output drive capability 50 Ω transmission lines at 85 °C

? Complies with JEDEC standard JESD8-B