74ALVT162823DGG集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

1 General description

The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra

packages required to buffer existing registers and provide extra data width for wider data

or address paths of buses carrying parity.

The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and

master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed

systems.

The registers are fully edge-triggered. The state of each D input, one set-up time before

the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the

flip-flop.

The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and

pull-down output structures. This design reduces line noise in applications such as

memory address drivers, clock drivers, and bus receivers or transmitters.

2 Features and benefits

? Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops

? 5 V I/O compatible

? Ideal where high speed, light loading or increased fan-in are required with MOS

microprocessors

? Bus hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

? Live insertion and extraction permitted

? Power-up 3-state

? Power-up reset

? Output capability: +12 mA to ?12 mA

? Outputs include series resistance of 30 Ω making external termination resistors

unnecessary

? Latch-up protection:

– JESD78: exceeds 500 mA

? ESD protection:

– MIL STD 883, method 3015: exceeds 2000 V

– MM: exceeds 200 V