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74ALVT16501中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書
廠商型號(hào) |
74ALVT16501 |
參數(shù)屬性 | 74ALVT16501 封裝/外殼為56-TFSOP(0.240",6.10mm 寬);包裝為管件;類別為集成電路(IC) > 通用總線功能;產(chǎn)品描述:IC UNIV BUS TXRX 18BIT 56TSSOP |
功能描述 | 18-bit universal bus transceiver; 3-state |
文件大小 |
231.55 Kbytes |
頁面數(shù)量 |
21 頁 |
生產(chǎn)廠商 | Nexperia B.V. All rights reserved |
企業(yè)簡(jiǎn)稱 |
NEXPERIA【安世】 |
中文名稱 | 安世半導(dǎo)體(中國(guó))有限公司官網(wǎng) |
原廠標(biāo)識(shí) | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2024-11-7 22:30:00 |
74ALVT16501規(guī)格書詳情
1. General description
The 74ALVT16501 is a high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) product designed for VCC operation at 2.5 V and 3.3 V with
I/O compatibility up to 5 V. This device is an 18-bit universal transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the
outputs are in the high-impedance state.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).
2. Features
n 18-bit bidirectional bus interface
n 5 V I/O compatible
n 3-state buffers
n Output capability: +64 mA to -32 mA
n TTL and LVTTL input and output switching levels
n Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
n Live insertion and extraction permitted
n Power-up reset
n Power-up 3-state
n No bus current loading when output is tied to 5 V bus
n Positive-edge triggered clock inputs
n Latch-up protection:
u JESD78: exceeds 500 mA
n ESD protection:
u MIL STD 883, method 3015: exceeds 2000 V
u Machine model: exceeds 400 V
產(chǎn)品屬性
- 產(chǎn)品編號(hào):
74ALVT16501DGG,118
- 制造商:
NXP USA Inc.
- 類別:
集成電路(IC) > 通用總線功能
- 系列:
74ALVT
- 包裝:
管件
- 邏輯類型:
通用總線收發(fā)器
- 電路數(shù):
18 位
- 電流 - 輸出高、低:
8mA,24mA;32mA,64mA
- 電壓 - 供電:
2.3V ~ 2.7V,3V ~ 3.6V
- 工作溫度:
-40°C ~ 85°C
- 安裝類型:
表面貼裝型
- 封裝/外殼:
56-TFSOP(0.240",6.10mm 寬)
- 供應(yīng)商器件封裝:
56-TSSOP
- 描述:
IC UNIV BUS TXRX 18BIT 56TSSOP
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
PHI |
2020+ |
TSSOP |
80000 |
只做自己庫存,全新原裝進(jìn)口正品假一賠百,可開13%增 |
詢價(jià) | ||
NXP/恩智浦 |
23+ |
NA/ |
1000 |
優(yōu)勢(shì)代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價(jià) | ||
NXP/恩智浦 |
20+ |
SSOP56 |
9850 |
只做原裝正品假一賠十為客戶做到零風(fēng)險(xiǎn)!! |
詢價(jià) | ||
PHI |
SSOP56 |
68500 |
一級(jí)代理 原裝正品假一罰十價(jià)格優(yōu)勢(shì)長(zhǎng)期供貨 |
詢價(jià) | |||
NXP/恩智浦 |
22+ |
SSOP |
12245 |
現(xiàn)貨,原廠原裝假一罰十! |
詢價(jià) | ||
PHI原裝現(xiàn)貨 |
21+ |
TSSOP |
875 |
原裝現(xiàn)貨假一賠十 |
詢價(jià) | ||
NXP |
22+ |
56SSOP |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價(jià) | ||
PHILIPS |
22+ |
TSOP56 |
2987 |
只售原裝自家現(xiàn)貨!誠(chéng)信經(jīng)營(yíng)!歡迎來電! |
詢價(jià) | ||
NXP/恩智浦 |
22+ |
SSOP |
50000 |
只做原裝正品,假一罰十,歡迎咨詢 |
詢價(jià) | ||
NXP/恩智浦 |
22+ |
SSOP56 |
9852 |
只做原裝正品現(xiàn)貨,或訂貨假一賠十! |
詢價(jià) |